This invention relates to a bipolar transistor and its manufacturing method.
Now that larger-size and higher performance LSIs are demanded more and more performance of bipolar transistors is also demanded to be more enhanced These days.
In order to meet such a demand for bipolar transistors, the base width of the target bipolar transistor has been narrowed to shorten the base transit time, the base resistance has been reduced, and the parasitic capacity represented by the capacity formed between base and collector has been reduced.
In a bipolar transistor adopting a so-called double polysilicon structure in which the emitter output electrode and the base output electrode are made of 2-layer polysilicon, each emitter output electrode is separated from each base output electrode by a side wall insulating film to reduce the base-collector capacity significantly.
Furthermore, in order to shorten the base transit time, a shallow base junction has been materialized to reduce the base width by low energy ion implantation technology.
Furthermore, recently, another technology for forming the base layer by epitaxial technology (so-called Epi-Base technology) was proposed to reduce both the base width and the base resistance simultaneously.
Hereunder, an embodiment of a double polysilicon structure bipolar transistor that uses the Epi-Base technology will be described briefly with reference to FIG. 1A through FIG. 1D. The transistor was disclosed in Japanese Patent Laid Open No.159726/1990.
As shown in FIG. 1A, an n+ type embedded layer 212 is formed on a P type silicon substrate 211, and an n type epitaxial layer 213 is formed above the p type silicon substrate 211.
After this, a so-called trench-like element separating area 214 is formed in the n type epitaxial layer 213 by selective non-isotropic etching and embedding technology of insulating film. This element separating area 214 separates an element forming area 215 from others. In the deep element separating area 214 is embedded a polysilicon layer 216 as shown in FIG. 1A. Then, an n+ type collector output diffusion layer 241 is formed and connected to the n+ type embedded layer 212.
Subsequently, an oxidized silicon film 217 is formed on the entire surface of the n type epitaxial layer 213 using the Chemical Vapor Deposition (CVD) method.
After this, the oxidized silicon film 217 is removed from the element forming area 215 by lithographic technology and by etching technology to form first opening 218.
The resist mask (not illustrated) formed by lithographic technology is removed after the etching is ended. Hereafter, in the same process, each resist mask is regarded to be removed after etching is ended.
Subsequently, an epitaxial layer 219 to be used as a p type semiconductor layer is formed inside the first opening 218 by selective epitaxial growth. This epitaxial layer 219 is made of, for example, silicon (Si), germanium (Ge), silicon germanium (Si.sub.1-x Ge.sub.x), and the like into which P type impurities such as boron (B) are implanted.
When oxidized silicon is used for the insulating film, the surfaces of both the p type epitaxial layer 219 and the oxidized silicon film 217 can be almost flattened if the insulating film is formed selectively only on the n type epitaxial layer 213. In this case, the insulating film does not make any epitaxial growth on the oxidized silicon film in the epitaxial growth process.
On the other hand, if a p type epitaxial layer 219 is formed on the oxidized silicon film 217, a single crystal layer is formed on the n type epitaxial layer 213 and a poly-crystal layer is formed on the oxidized silicon film 217. FIG. 1A shows such a case in which a poly-crystal layer is formed.
After this, as shown in FIG. 1B, an insulating film 220 of oxidized silicon film is formed all over the surface with the CVD method.
Then, second opening 221 is formed on the insulating film 220 by lithographic technology and by etching technology so that the opening may be positioned on the p type epitaxial layer 219. At the bottom of this second opening 221 is thus exposed the end of the p type epitaxial layer 219 by a width of L.sub.1. The second opening 221 is formed so that part of it may overlap with the element separating area 214 in the top view of the substrate.
Consequently, the surface of the p type epitaxial layer 219 is exposed at the bottom of the second opening 221 by a width of L.sub.1.
Subsequently, a polysilicon layer 222 is formed on the entire surface of the object with the CVD method. This polysilicon layer 222 functions as a base output electrode and covers the insulating film 220 on which the second opening 221 is formed. Especially, the polysilicon layer 222 is connected to the surface of the p type epitaxial layer 219 at the bottom of the second opening 221.
Ion implantation can also be used for doping for the polysilicon layer 222.
After this, a resist mask is formed by lithographic technology and the mask is used for dry-etching for patterning the polysilicon layer 222.
The patterned polysilicon layer 222 is then covered by forming an oxidized silicon layer 223.
Then, a resist layer 225 is formed by lithographic technology, and an opening 226 is formed on the resist layer 225. The opening 226 is formed in the upper portion inside the insulating film 220 formed above the p type epitaxial layer 219. For example, the opening inside the insulating film 220 is away from the edge of the second opening 221 by a width of L.sub.2.
Subsequently, as shown in FIG. 1C, third opening 224 is formed by non-isotropic etching (reactive ion etching) using the resist layer 225 as a mask so that the opening may go through the insulating film 223, the polysilicon layer 222, and the insulating film 220. This third opening 224 is formed by copying the shape of the opening 226.
After this, ion implantation is performed to form an n+ type deep impurity area 242 near the boundary between the n type embedded layer 212 and the n type epitaxial layer 213 formed under the p type epitaxial layer 219.
Subsequently, an oxidized silicon film is formed all over the impurity area 242 with the CVD method to form a side wall insulating film. Then, the oxidized silicon film is etched back to form a side wall insulating film 227 on the side wall of the third opening 224. The side wall insulating film 227 is also used as a side wall insulating film.
After this, as shown in FIG. 1D, a thin polysilicon layer 228 is formed on the side wall of the side wall insulating film 227 with the CVD method, for example. Then, n type impurities are ion-implanted in the polysilicon layer 228, then an emitter layer 230 is formed by diffusion of impurities from the polysilicon layer 228.
In the thermal treatment performed at this time, a graft base layer 229 is also formed together by diffusion of impurities from the polysilicon layer 222. The polysilicon layer 228 functions as an emitter lead electrode.
Hereafter, no illustration will be used for explaining the subsequent processes.
At first, contact holes are formed to output signals from collector and base, then base electrodes, emitter electrodes, and collector electrodes are formed to finish the manufacturing of the target bipolar transistor.
However, there are still many problems that cannot be solved by the prior art technologies described above. Hereunder, therefore, the problems that this invention is to solve will be explained using the codes given to the configuration items in FIG. 1A through FIG. 1D for explaining the prior art technologies.
In other words, when forming a p type epitaxial layer 219 used as a base layer in an epitaxial growth process, a problem arises from the crystallinity property of the epitaxial layer 219. The epitaxial layer 219 formed by selective epitaxial growth deteriorates the crystallinity at the edge of the first opening 218. Thus, a large current leaks from the pn junction formed at this portion.
Consequently, the pn junction must avoid the end of the epitaxial layer 219 and this becomes a restriction for forming elements.
Concretely, a certain distance must be secured between a junction between a graft base layer 229 and an N type epitaxial layer 213 used as a collector area, and the edge of the first opening 218 when the graft base 229 is to be formed. And for this purpose, the diffusion depth of the graft base layer 219 had to be larger than the film thickness of the P type epitaxial layer 219.
However, since the graft base layer 229 was formed by diffusion of impurities from the polysilicon layer 222, a high temperature thermal treatment was needed for forming a diffusion layer deeper than the film thickness of the P type epitaxial layer 219. For example, if the P type epitaxial layer 219 has a film thickness of 50 to 100 nm, a thermal treatment of 10 to 30 minutes had to be performed at 900.degree. C. so as to form a graft base layer having a diffusion depth of 100 to 200 nm. If such a thermal treatment is performed, however, impurities in the base layer [P type epitaxial layer 219] are also diffused at the same time. This was why the merit of a shallow junction base formed in an epitaxial growth process was lost.
The object of this invention is thus to provide a high performance bipolar transistor with excellent characteristics by preventing epitaxial layers from current leaking without disturbing the shallow junction base layer formed in an epitaxial growth process, as well as to provide a manufacturing method for such transistors.